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HY62SF16101C Series
64Kx16bit full CMOS SRAM
Document Title
64K x16 bit 1.8V Super Low Power Full CMOS Slow SRAM
Revision History
Revision No 03 History Divide output load into a couple of factors - tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW - Others Add marking information Change AC Characteristic - tBLZ Draft Date Dec.16. 2000 Remark Final
04
Mar.24. 2002
Final
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.04 /Mar. 02 Hynix Semiconductor
HY62SF16101C Series DESCRIPTION
The HY62SF16101C is a high speed, super low power and 1M bit full CMOS SRAM organized as 65,536 words by 16bit. The HY62SF16101C uses high performance full CMOS process technology and designed for high speed low power circuit technology. It is particularly well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
FEATURES
* Fully static operation and Tri-state output * TTL compatible inputs and outputs * Battery backup(LL/SL-part) -. 1.2V(min) data retention * Standard pin configuration -. 48 - FBGA
Product Voltage Speed No. (V) (ns) HY62SF16101C 1.7~2.3 85/100/120 HY62SF16101C-I 1.7~2.3 85/100/120 Note 1. Blank : Commercial, I : Industrial 2. Current value is max.
Operation Current/Icc(mA) 3 3
Standby Current(uA) LL SL 2 1 2 1
Temperature (C) 0~70 -40~85(I)
PIN CONNECTION
/LB /OE A0 A1 A4 A6 A7 NC A2 NC
A0
BLOCK DIAGRAM
ROW DECODER SENSE AMP ADD INPUT BUFFER I/O1
IO9 /UB A3 IO10 IO11 A5 Vss IO12 NC Vcc IO13 NC
/CS IO1 IO2 IO3 IO4 Vcc IO5 Vss
COLUMNDECODER
DATA I/O BUFFER
IO15 IO14 A14 A15 IO6 IO7 IO16 NC NC A8 A12 A13 /WE IO8 A9 A10 A11 NC
A15
MEMORY ARRAY 128K x 16
WRITE DRIVER
I/O16
48-FBGA(Top View)
/CS /OE /LB /UB /WE
CONTROL LOGIC
PIN DESCRIPTION
Pin Name /CS /WE /OE /LB /UB Pin Function Chip Select Write Enable Output Enable Low Byte Control(I/O1~I/O8) Upper Byte Control(I/O9~I/O16) Pin Name I/O1~I/O16 A0~A15 Vcc Vss NC Pin Function Data Inputs/Outputs Address Inputs Power(1.7V~2.3V) Ground No Connection
Rev.04 /Mar. 02
2
HY62SF16101C Series
ORDERING INFORMATION
Part No. HY62SF16101CLLF HY62SF16101CSLF HY62SF16101CLLF-I HY62SF16101CSLF-I Speed 85/100/120 85/100/120 85/100/120 85/100/120 Power LL-part SL-part LL-part SL-part Temp. FBGA FBGA FBGA FBGA Package
I. I.
Note 1. Blank : Commercial, I : Industrial
ABSOLUTE MAXIMUM RATING (1)
Symbol VIN, VOUT Vcc TA TSTG PD TSOLDER Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Lead Soldering Temperature & Time Rating -0.2 to 3.6 -0.2 to 4.6 0 to 70 -40 to 85 -55 to 150 1.0 260 10 Unit V V C C C W C sec Remark
HY62SF16101C HY62SF16101C-I
Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS H X L L L /WE X X H H H /OE X X H H L /LB X H L X L H L L H L /UB X H X L H L L H L L Mode Deselected Deselected Output Disabled Output Disabled Read I/O I/O1~I/O8 High-Z High-Z High-Z High-Z DOUT Hi-Z DOUT DIN Hi-Z DIN I/O9~I/O16 High-Z High-Z High-Z High-Z Hi-Z DOUT DOUT Hi-Z DIN DIN Power Stand by Stand by Active Active Active
L
L
X
Write
Active
Note: 1. H=VIH, L=VIL, X=don't care(VIH or VIL) 2. /UB, /LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When /LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8. When /UB is LOW, data is written or read to the Upper byte, I/O 9 -I/O 16.
Rev.04 /Mar. 02
2
HY62SF16101C Series RCOMMENDED DC OPERATING CONDITION
Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 1.7 0 1.4 -0.3(1) Typ. 1.8 0 Max. 2.3 0 Vcc+0.3 0.4 Unit V V V V
Note : 1. VIL = -1.5V for pulse width less than 30ns 2. Undershoots are sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
Vcc = 1.7V~2.3V, TA = 0C to 70C / -40C to 85C (I) Sym Parameter Test Condition ILI Input Leakage Current Vss < VIN < Vcc ILO Output Leakage Current Vss < VOUT < Vcc, /CS = VIH or /OE = VIH or /WE = VIL, /UB = /LB = VIH Icc Operating Power Supply /CS = VIL, VIN = VIH or VIL, Current II/O = 0mA ICC1 Average Operating Current /CS < 0.2V, 1us Cycle Time,100% Duty, II/O = 0mA, VIN < 0.2V /CS = VIL, VIN = VIH or VIL Cycle Time = Min. 100% Duty II/O = 0mA ISB TTL Standby Current /CS = VIH or (TTL Input) /UB = /LB = VIH, VIN = VIH or VIL ISB1 Standby Current /CS > Vcc - 0.2V or SL (CMOS Input) /UB = /LB > Vcc - 0.2V, VIN > Vcc - 0.2V or LL VIN < Vss + 0.2V VOL Output Low Voltage IOL = 0.1mA VOH Output High Voltage IOH = -0.1mA Note : 1.Typical values are at Vcc = 1.8V, TA = 25C 2.Typical values are sampled and not 100% tested. Min. -1 -1 Typ. Max. 1 1 Unit uA uA
-
-
3 3
mA mA
-
-
25
mA
1.6
0.5 -
0.3 1 2 0.2 -
mA uA uA V V
CAPACITANCE
(Temp = 25C, f= 1.0MHz) Symbol Parameter CIN Input Capacitance(Add, /CS, /UB, /LB, /WE, /OE) COUT Output Capacitance(I/O) Note : These parameters are sampled and not 100% tested Condition VIN = 0V VI/O = 0V Max. 8 10 Unit pF pF
Rev.04 /Mar. 02
3
HY62SF16101C Series AC CHARACTERISTICS
Vcc = 1.7~2.3V, TA = 0C to 70C / -40C to 85C (I) , unless otherwise specified -85 -10 # Symbol Parameter Min. Max. Min. Max. READ CYCLE 1 tRC Read Cycle Time 85 100 2 tAA Address Access Time 85 100 3 tACS Chip Select Access Time 85 100 4 tOE Output Enable to Output Valid 40 45 5 tBA /LB, /UB Access Time 85 100 6 tCLZ Chip Select to Output in Low Z 10 20 7 tOLZ Output Enable to Output in Low Z 5 5 8 tBLZ /LB, /UB Enable to Output in Low Z 10 10 9 tCHZ Chip Deselection to Output in High Z 0 30 0 30 10 tOHZ Out Disable to Output in High Z 0 30 0 30 11 tBHZ /LB, /UB Disable to Output in High Z 0 30 0 30 12 tOH Output Hold from Address Change 10 15 WRITE CYCLE 13 tWC Write Cycle Time 85 100 14 tCW Chip Selection to End of Write 70 80 15 tAW Address Valid to End of Write 70 80 16 tBW /LB, /UB Valid to End of Write 70 80 17 tAS Address Set-up Time 0 0 18 tWP Write Pulse Width 55 75 19 tWR Write Recovery Time 0 0 20 tWHZ Write to Output in High Z 0 30 0 35 21 tDW Data to Write Time Overlap 35 45 22 tDH Data Hold from Write Time 0 0 23 tOW Output Active from End of Write 5 10 Min 120 20 10 20 0 0 0 15 120 100 100 100 0 85 0 0 50 0 10 -12 Max. 120 120 50 120 40 40 40 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AC TEST CONDITIONS
TA = 0C to 70C / -40C to 85C (I), unless otherwise specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW Others Value 0.4V to 1.6V 5ns 0.9V CL = 5pF + 1TTL Load CL = 30pF + 1TTL Load
AC TEST LOADS
VTM=1.8V
4091 Ohm DOUT CL(1) 3273 Ohm
Note 1. Including jig and scope capacitance
Rev.04 /Mar. 02
4
HY62SF16101C Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC ADDR tAA tACS /CS tCHZ(3) tBA /UB ,/ LB tOE tOLZ(3) tBLZ(3) tCLZ(3) Data Valid tBHZ(3) tOH
/OE
tOHZ(3)
Data Out
High-Z
READ CYCLE 2(Note 1,2,4)
tRC ADDR tAA tOH Data Out Previous Data Data Valid tOH
READ CYCLE 3(Note 1,2,4)
/CS /UB, /LB
tACS tCLZ(3) Data Out Data Valid tCHZ(3)
Notes: 1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and low /UB and/or /LB. 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS in high for the standby, low for active /UB and /LB in high for the standby, low for active
Rev.04 /Mar. 02
5
HY62SF16101C Series
WRITE CYCLE 1(1,4,8) (/WE Controlled)
tWC ADDR tWR(2) tCW /CS tAW tBW /UB,/LB tWP /WE tAS Data In High-Z tWHZ(3,7) Data Out tDW Data Valid tOW (5) (6) tDH
WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled)
tWC ADDR tAS /CS tAW tBW /UB,/LB tWP /WE tDW Data In High-Z Data Valid tDH tCW tWR(2)
Data Out
High-Z
Notes: 1. A write occurs during the overlap of a low /WE, a low /CS1 and low /UB and/or /LB. 2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. Transition is measured +200mV from steady state. This parameter is sampled and not 100% tested. 8. /CS in high for the standby, low for active /UB and /LB in high for the standby, low for active
Rev.04 /Mar. 02
6
HY62SF16101C Series DATA RETENTION ELECTRIC CHARACTERISTIC
TA=0C to 70C / -40C to 85C (I) Symbol Parameter VDR Vcc for Data Retention Test Condition /CS > Vcc - 0.2V or /UB = /LB > Vcc-0.2V, VIN > Vcc - 0.2V or VIN < Vss + 0.2V Vcc=1.5V, /CS > Vcc - 0.2V or LL /UB = /LB > Vcc-0.2V, VIN > Vcc - 0.2V or SL VIN < Vss + 0.2V See Data Retention Timing Diagram Min 1.2 Typ Max 2.3 Unit V
ICCDR
Data Retention Current
0 tRC(2)
0.5 -
2 1 -
uA uA ns ns
tCDR tR
Chip Deselect to Data Retention Time Operating Recovery Time
Notes: 1. Typical values are under the condition of TA = 25C. 2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
VCC 1.7V tCDR DATA RETENTION MODE tR
VDR CS or /UB &/LB VSS CS > VCC-0.2V or /UB = /LB > Vcc - 0.2V
Rev.04 /Mar. 02
7
HY62SF16101C Series
PACKAGE INFORMATION
48ball Fine-Pitch Ball Grid Array Package(F)
BOTTOM VIEW
B A A1 CORNER INDEX AREA 6 A A B C D C E F G H C1/2 C1/2 C1 5 4 3 2 1 B1/2
TOP VIEW
B1/2
B1
SIDE VIEW
5
C
E1 E2 E SEATING PLANE A 4
r
3 D(DIAMETER)
Note
Symbol A B B1 C C1 D E E1 E2 r
Min. 6.1 6.2 0.3 0.9 0.7 0.2 -
Typ. 0.75 3.75 6.2 5.25 6.3 0.35 1.0 0.75 0.25 -
Max. 6.3 6.4 0.4 1.1 0.8 0.3 0.1
1. DIMENSIONING AND TOLERANCING PER ASME Y14. SM-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION "D" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. THIS IS A CONTROLLING DIMENSION.
Rev.04 /Mar. 02
8
HY62SF16101C Series MARKING INSTRUCTION
Package
H Y
Marking Example
S F 6 1 1 C c
FBGA
s
s
t
y
y
w
w
p
x
x
x
x
x
K
O
R
Index
* HYSF611Cc c : Part Name : Power Consumption -L -S : Speed - 85 - 10 - 12 *t : Temperature -C -I : 85ns : 100ns : 120ns : Industrial ( -0 ~ 70 C ) : Industrial ( -40 ~ 85 C ) : Low Low Power : Super Low Power
* ss
* yy * ww *p * xxxxx * KOR Note - Capital Letter - Small Letter
: Year (ex : 00 = year 2000, 01= year 2001) : Work Week ( ex : 12 = work week 12 ) : Process Code : Lot No. : Origin Country
: Fixed Item : Non-fixed Item
Rev.04 /Mar. 02
9

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